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timing debug #908

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timing debug #908

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qinjun-li
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  • [rtl] merge csrInterface to laneRequest.
  • [rtl] connect laneRequest with shifter.
  • [rtl] connect vrf read with shifter.
  • [rtl] Pipe result in float adder.
  • [rtl] connect vrf write with shifter.
  • [rtl] add mask control.
  • [rtl] duplicate v0 in lsu.
  • [om] bug fix on the ReferenceTarget pattern match
  • [om] retime FloatAdder in Permutation
  • [rtl] fix mask update in lane.
  • [code] format.
  • [rtl] fix vrf read result.
  • [rtl] Check whether the order of instruction index is clear in the sequencer.
  • [rtl] Pipe result in MaskCompress.
  • [rtl] Add read token in store unit.
  • [rtl] retime compress unit.
  • [rtl] retime compress unit.
  • [rtl] cut pipe in compress unit.
  • [rtl] pipe instructionFinished in sequencer.

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